1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Background Art
Research and development have been conducted pertaining to a semiconductor memory device in which memory cells including variable resistance elements are arranged in an array.
For instance, a PCRAM (Phase-Change Random Access Memory, or phase-change memory) utilizing chalcogenide elements as variable resistance elements has been known.
In the PCRAM, the temperature of a chalcogenide element configuring a memory cell is controlled by changing current/voltage to be applied to a selected memory cell, and information is recorded (written) by phase-changing the chalcogenide element to a crystalline state or a noncrystalline state. The resistance value of the chalcogenide element in the amorphous state is higher than that in the crystalline state. Accordingly, the resistance value of the chalcogenide element configuring the memory cell is detected by a circuit, thereby allowing reading of written information.
As another semiconductor memory device using a variable resistance element, a ReRAM (Resistance Random Access Memory) using a transition metal oxide element, and a CBRAM (Conductive Bridging Random Access Memory) that changes the resistance by precipitating metal cations to form a bridge (conducting bridge) between electrodes and ionizing the precipitated metal to destruct the bridge have been known (see JP Patent Publication (Kokai) No. 2009-217908A (2009)).
These semiconductor memory devices are capable of maintaining stored information in nonvolatile manner even after breaking of power source. A writing operation that changes a variable resistance element in a memory cell from a high resistance state to a low resistance state is referred to as “set”; the operation that changes the element from the low resistance state to the high resistance state is referred to as “reset”. Some proposals have been made on circuits for setting or resetting.
JP Patent Publication (Kokai) No. 2009-217908A (2009) aims at preventing failed data write or failed data erase from occurring in setting or resetting operation on a memory cell by means of including a current limit circuit that limits the value of current flowing in the memory cell in writing data to a prescribed current limit value. JP Patent Publication (Kohyo) Nos. 2006-514392A (2006) and 2006-514440A (2006) aim at securing a read/write margin even if unevenness in distribution of low and high resistance values of memory cells becomes large, by means of including a write circuit that selects two neighboring memory cells in a cell array in a 3D phase-change memory as a pair cell and writes to cause one and the other of the pair cell to be high and low resistance value states, respectively, and read circuit that reads the complementary resistance value states of the pair cell as one-bit data. JP Patent Publication (Kokai) No. 2008-165964A (2008) aims at limiting a peak power consumption in writing on a phase-change memory by means of receiving a first current to program a plurality of resistance memory cells, limiting this current, and supplying a pulse generator with stored charge as a second current.
A related technical document, IEEE International Electron Devices Meeting, 2007, pp. 449-452, “Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory”, discloses a multilayer flash memory technology and describes an idea allowing the planar density of memory cells to be 4 F2.
Problems to be solved by the present invention are important in semiconductor memory devices using variable resistance elements for allowing memory cells to be finer and highly integrated, that is, improving scaling. More specifically, three problems will be described later. These problems are not considered in the above cited documents, which do not discuss effects of parasitic resistance and parasitic capacitance from a driver circuit to a memory cell. Hereinafter, for the sake of simplicity, the memory cell and the memory cell array are simply referred to as a cell and an array, respectively, in some cases.
A first problem is that heat generated in a selected cell is conducted to a not-selected cell and this varies and degrades the resistance value of a variable resistance element in the not-selected cell. The separation between cells is reduced with improvement in scaling. As a result, Joule heat is generated by application of a current to the selected cell in setting or resetting to neighboring not-selected cells. Accordingly, it is concerned that the states of the variable resistance elements in the neighboring cells are partially changed and, at worst, large variation in resistance value reverses stored information. This specification refers to this phenomenon as thermal disturbance to a non-selected memory cell.
A second problem is a loss and unevenness of write voltage. Improvement in scaling makes wiring from a write circuit to a memory cell array finer, thereby increasing the resistance value. Accordingly, in a writing operation, when a voltage is applied from the write circuit to a selected cell in the array, the voltage is dropped owing to the wiring resistance and thus the voltage to be applied to the cell becomes lower than that generated in the write circuit. The distance between the write circuit and the selected cell is different according to the position of the cell on a semiconductor chip, thereby increasing unevenness of voltage drop accordingly.
As a result of the voltage drop not only reduces the current flowing to the cell but also varies the amount thereof. Thus, the write current to the cell varies according to the position on the chip, and stable operation becomes difficult.
A third problem is reduction in read speed. As described above, a reading operation of the semiconductor memory device using the variable resistance element requires detecting the magnitude of the resistance of the variable resistance element in the cell. For the sake thereof, the magnitude of current flowing by application of a voltage to the variable resistance element in the selected cell is typically detected.
However, application of a voltage and a current close to those required for writing causes a fear that changes or reverses the state of the variable resistance element in the cell. Accordingly, in order not to rewrite the state of the variable resistance element, the voltage and the current for reading is preferably smaller than those to be applied in writing. As a result, it becomes difficult to speed up transmission of a read signal of the memory cell from the array to a read circuit. For instance, the speed of driving a wiring, referred to as a bit line, by a current flowing to a memory cell is limited by the current capable of flowing to the memory cell and the parasitic capacitance of the bit line. In a case where improvement in scaling reduces the distance between the memory cells, the pitch of the bit lines becomes narrower. This increases the parasitic capacitance of the bit line, thereby reducing the read speed.
The problems, which become serious with improvement in scaling in a semiconductor memory device using a variable resistance element, are not well considered in the reference documents.